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jwanggit86jwanggit86
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Futher changes to tableGen to ensure disassembler works.
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6 files changed

+165
-13
lines changed

6 files changed

+165
-13
lines changed

‎llvm/lib/Target/AMDGPU/SIInstructions.td

Lines changed: 88 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -2465,6 +2465,7 @@ def : AMDGPUPat <
24652465
>;
24662466

24672467
let True16Predicate = NotHasTrue16BitInsts in {
2468+
let SubtargetPredicate = isNotGFX9Plus in {
24682469
def : ROTRPattern <V_ALIGNBIT_B32_e64>;
24692470

24702471
def : GCNPat<(i32 (trunc (srl i64:$src0, (and i32:$src1, (i32 31))))),
@@ -2474,6 +2475,62 @@ def : GCNPat<(i32 (trunc (srl i64:$src0, (and i32:$src1, (i32 31))))),
24742475
def : GCNPat<(i32 (trunc (srl i64:$src0, (i32 ShiftAmt32Imm:$src1)))),
24752476
(V_ALIGNBIT_B32_e64 (i32 (EXTRACT_SUBREG (i64 $src0), sub1)),
24762477
(i32 (EXTRACT_SUBREG (i64 $src0), sub0)), $src1)>;
2478+
} // isNotGFX9Plus
2479+
2480+
let SubtargetPredicate = isGFX9GFX10 in {
2481+
def : GCNPat <
2482+
(rotr i32:$src0, i32:$src1),
2483+
(V_ALIGNBIT_B32_opsel_e64 /* src0_modifiers */ 0, $src0,
2484+
/* src1_modifiers */ 0, $src0,
2485+
/* src2_modifiers */ 0,
2486+
$src1, /* clamp */ 0, /* op_sel */ 0)
2487+
>;
2488+
2489+
foreach pat = [(i32 (trunc (srl i64:$src0, (and i32:$src1, (i32 31))))),
2490+
(i32 (trunc (srl i64:$src0, (i32 ShiftAmt32Imm:$src1))))] in
2491+
def : GCNPat<pat,
2492+
(V_ALIGNBIT_B32_opsel_e64 0, /* src0_modifiers */
2493+
(i32 (EXTRACT_SUBREG (i64 $src0), sub1)),
2494+
0, /* src1_modifiers */
2495+
(i32 (EXTRACT_SUBREG (i64 $src0), sub0)),
2496+
0, /* src2_modifiers */
2497+
$src1, /* clamp */ 0, /* op_sel */ 0)
2498+
>;
2499+
2500+
//def : GCNPat<(i32 (trunc (srl i64:$src0, (and i32:$src1, (i32 31))))),
2501+
// (V_ALIGNBIT_B32_opsel_e64 0, /* src0_modifiers */
2502+
// (i32 (EXTRACT_SUBREG (i64 $src0), sub1)),
2503+
// 0, /* src1_modifiers */
2504+
// (i32 (EXTRACT_SUBREG (i64 $src0), sub0)),
2505+
// 0, /* src2_modifiers */
2506+
// $src1, /* clamp */ 0, /* op_sel */ 0)
2507+
//>;
2508+
2509+
//def : GCNPat<(i32 (trunc (srl i64:$src0, (and i32:$src1, (i32 31))))),
2510+
// (V_ALIGNBIT_B32_opsel_e64 0, /* src0_modifiers */
2511+
// (i32 (EXTRACT_SUBREG (i64 $src0), sub1)),
2512+
// 0, /* src1_modifiers */
2513+
// (i32 (EXTRACT_SUBREG (i64 $src0), sub0)),
2514+
// 0, /* src2_modifiers */
2515+
// $src1, /* clamp */ 0, /* op_sel */ 0)
2516+
//>;
2517+
2518+
//def : GCNPat<(i32 (trunc (srl i64:$src0, (i32 ShiftAmt32Imm:$src1)))),
2519+
// (V_ALIGNBIT_B32_opsel_e64 0, /* src0_modifiers */
2520+
// (i32 (EXTRACT_SUBREG (i64 $src0), sub1)),
2521+
// 0, /* src1_modifiers */
2522+
// (i32 (EXTRACT_SUBREG (i64 $src0), sub0)),
2523+
// 0, /* src2_modifiers */
2524+
// $src1, /* clamp */ 0, /* op_sel */ 0)
2525+
//>;
2526+
2527+
def : GCNPat<(fshr i32:$src0, i32:$src1, i32:$src2),
2528+
(V_ALIGNBIT_B32_opsel_e64 /* src0_modifiers */ 0, $src0,
2529+
/* src1_modifiers */ 0, $src1,
2530+
/* src2_modifiers */ 0,
2531+
$src2, /* clamp */ 0, /* op_sel */ 0)
2532+
>;
2533+
} // isGFX9GFX10
24772534
} // end True16Predicate = NotHasTrue16BitInsts
24782535

24792536
let True16Predicate = UseRealTrue16Insts in {
@@ -3549,15 +3606,41 @@ def : GCNPat <
35493606

35503607
// Take the upper 16 bits from V[0] and the lower 16 bits from V[1]
35513608
// Special case, can use V_ALIGNBIT (always uses encoded literal)
3552-
let True16Predicate = NotHasTrue16BitInsts in
3553-
def : GCNPat <
3609+
let True16Predicate = NotHasTrue16BitInsts in {
3610+
3611+
defvar BuildVectorToAlignBitPat =
35543612
(vecTy (DivergentBinFrag<build_vector>
35553613
(Ty !if(!eq(Ty, i16),
35563614
(Ty (trunc (srl VGPR_32:$a, (i32 16)))),
35573615
(Ty (bitconvert (i16 (trunc (srl VGPR_32:$a, (i32 16)))))))),
3558-
(Ty VGPR_32:$b))),
3559-
(V_ALIGNBIT_B32_e64 VGPR_32:$b, VGPR_32:$a, (i32 16))
3560-
>;
3616+
(Ty VGPR_32:$b)));
3617+
3618+
let SubtargetPredicate = isNotGFX9Plus in
3619+
def : GCNPat<BuildVectorToAlignBitPat, (V_ALIGNBIT_B32_e64 VGPR_32:$b, VGPR_32:$a, (i32 16))>;
3620+
3621+
let SubtargetPredicate = isGFX9GFX10 in
3622+
def : GCNPat<BuildVectorToAlignBitPat, (V_ALIGNBIT_B32_opsel_e64 0, VGPR_32:$b, 0, VGPR_32:$a, 0, (i32 16), 0, 0)>;
3623+
3624+
//let SubtargetPredicate = isNotGFX9Plus in
3625+
//def : GCNPat <
3626+
// (vecTy (DivergentBinFrag<build_vector>
3627+
// (Ty !if(!eq(Ty, i16),
3628+
// (Ty (trunc (srl VGPR_32:$a, (i32 16)))),
3629+
// (Ty (bitconvert (i16 (trunc (srl VGPR_32:$a, (i32 16)))))))),
3630+
// (Ty VGPR_32:$b))),
3631+
// (V_ALIGNBIT_B32_e64 VGPR_32:$b, VGPR_32:$a, (i32 16))
3632+
//>;
3633+
3634+
//let SubtargetPredicate = isGFX9GFX10 in
3635+
//def : GCNPat <
3636+
// (vecTy (DivergentBinFrag<build_vector>
3637+
// (Ty !if(!eq(Ty, i16),
3638+
// (Ty (trunc (srl VGPR_32:$a, (i32 16)))),
3639+
// (Ty (bitconvert (i16 (trunc (srl VGPR_32:$a, (i32 16)))))))),
3640+
// (Ty VGPR_32:$b))),
3641+
// (V_ALIGNBIT_B32_opsel_e64 0, VGPR_32:$b, 0, VGPR_32:$a, 0, (i32 16), 0, 0)
3642+
//>;
3643+
} //True16Predicate = NotHasTrue16BitInsts
35613644

35623645
let True16Predicate = UseFakeTrue16Insts in
35633646
def : GCNPat <

‎llvm/lib/Target/AMDGPU/VOP3Instructions.td

Lines changed: 6 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -219,7 +219,8 @@ defm V_ALIGNBIT_B32 : VOP3Inst_t16_with_profiles <"v_alignbit_b32",
219219

220220
defm V_ALIGNBYTE_B32 : VOP3Inst <"v_alignbyte_b32", VOP3_Profile<VOP_I32_I32_I32_I32>, int_amdgcn_alignbyte>;
221221

222-
// In gfx9 and 10, opsel is allowed for V_ALIGNBIT_B32 and V_ALIGNBYTE_B32
222+
// In gfx9 and 10, opsel is allowed for V_ALIGNBIT_B32 and V_ALIGNBYTE_B32.
223+
// Hardware uses opsel[1:0] to byte-select src2. Other opsel bits are ignored.
223224
defm V_ALIGNBIT_B32_opsel : VOP3Inst <"v_alignbit_b32_opsel", VOP3_Profile<VOP_I32_I32_I32_I32, VOP3_OPSEL>>;
224225
defm V_ALIGNBYTE_B32_opsel : VOP3Inst <"v_alignbyte_b32_opsel", VOP3_Profile<VOP_I32_I32_I32_I32, VOP3_OPSEL>>;
225226

@@ -2100,8 +2101,8 @@ defm V_BFI_B32 : VOP3_Real_gfx6_gfx7_gfx10<0x14a>;
21002101
defm V_FMA_F32 : VOP3_Real_gfx6_gfx7_gfx10<0x14b>;
21012102
defm V_FMA_F64 : VOP3_Real_gfx6_gfx7_gfx10<0x14c>;
21022103
defm V_LERP_U8 : VOP3_Real_gfx6_gfx7_gfx10<0x14d>;
2103-
defm V_ALIGNBIT_B32 : VOP3_Real_gfx6_gfx7_gfx10<0x14e>;
2104-
defm V_ALIGNBYTE_B32 : VOP3_Real_gfx6_gfx7_gfx10<0x14f>;
2104+
defm V_ALIGNBIT_B32 : VOP3_Real_gfx6_gfx7<0x14e>;
2105+
defm V_ALIGNBYTE_B32 : VOP3_Real_gfx6_gfx7<0x14f>;
21052106
defm V_MULLIT_F32 : VOP3_Real_gfx6_gfx7_gfx10<0x150>;
21062107
defm V_MIN3_F32 : VOP3_Real_gfx6_gfx7_gfx10<0x151>;
21072108
defm V_MIN3_I32 : VOP3_Real_gfx6_gfx7_gfx10<0x152>;
@@ -2274,8 +2275,10 @@ defm V_BFI_B32 : VOP3_Real_vi <0x1ca>;
22742275
defm V_FMA_F32 : VOP3_Real_vi <0x1cb>;
22752276
defm V_FMA_F64 : VOP3_Real_vi <0x1cc>;
22762277
defm V_LERP_U8 : VOP3_Real_vi <0x1cd>;
2278+
let SubtargetPredicate = isGFX8Only in {
22772279
defm V_ALIGNBIT_B32 : VOP3_Real_vi <0x1ce>;
22782280
defm V_ALIGNBYTE_B32 : VOP3_Real_vi <0x1cf>;
2281+
}
22792282
defm V_MIN3_F32 : VOP3_Real_vi <0x1d0>;
22802283
defm V_MIN3_I32 : VOP3_Real_vi <0x1d1>;
22812284
defm V_MIN3_U32 : VOP3_Real_vi <0x1d2>;

‎llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fshr.mir

Lines changed: 20 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,8 @@
11
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
22
# RUN: llc -mtriple=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GCN %s
33
# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GCN %s
4-
# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GCN %s
5-
# RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GCN %s
4+
# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX9 %s
5+
# RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX10 %s
66
# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefixes=GFX11 %s
77

88
---
@@ -24,6 +24,24 @@ body: |
2424
; GCN-NEXT: [[V_ALIGNBIT_B32_e64_:%[0-9]+]]:vgpr_32 = V_ALIGNBIT_B32_e64 [[COPY]], [[COPY1]], [[COPY2]], implicit $exec
2525
; GCN-NEXT: S_ENDPGM 0, implicit [[V_ALIGNBIT_B32_e64_]]
2626
;
27+
; GFX9-LABEL: name: fshr_s32
28+
; GFX9: liveins: $vgpr0, $vgpr1, $vgpr2
29+
; GFX9-NEXT: {{ $}}
30+
; GFX9-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
31+
; GFX9-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
32+
; GFX9-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
33+
; GFX9-NEXT: [[V_ALIGNBIT_B32_opsel_e64_:%[0-9]+]]:vgpr_32 = V_ALIGNBIT_B32_opsel_e64 0, [[COPY]], 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $exec
34+
; GFX9-NEXT: S_ENDPGM 0, implicit [[V_ALIGNBIT_B32_opsel_e64_]]
35+
;
36+
; GFX10-LABEL: name: fshr_s32
37+
; GFX10: liveins: $vgpr0, $vgpr1, $vgpr2
38+
; GFX10-NEXT: {{ $}}
39+
; GFX10-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
40+
; GFX10-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
41+
; GFX10-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
42+
; GFX10-NEXT: [[V_ALIGNBIT_B32_opsel_e64_:%[0-9]+]]:vgpr_32 = V_ALIGNBIT_B32_opsel_e64 0, [[COPY]], 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $exec
43+
; GFX10-NEXT: S_ENDPGM 0, implicit [[V_ALIGNBIT_B32_opsel_e64_]]
44+
;
2745
; GFX11-LABEL: name: fshr_s32
2846
; GFX11: liveins: $vgpr0, $vgpr1, $vgpr2
2947
; GFX11-NEXT: {{ $}}

‎llvm/test/CodeGen/AMDGPU/branch-folding-implicit-def-subreg.ll

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -766,10 +766,10 @@ define amdgpu_kernel void @f1(ptr addrspace(1) %arg, ptr addrspace(1) %arg1, i64
766766
; GFX90A-NEXT: renamable $vgpr10 = COPY renamable $sgpr22, implicit $exec
767767
; GFX90A-NEXT: renamable $vgpr12_vgpr13 = DS_READ_B64_gfx9 killed renamable $vgpr10, 0, 0, implicit $exec :: (load (s64) from %ir.8, addrspace 3)
768768
; GFX90A-NEXT: renamable $vgpr10 = COPY renamable $sgpr46, implicit $exec
769-
; GFX90A-NEXT: renamable $vgpr11 = V_ALIGNBIT_B32_e64 killed $sgpr47, killed $vgpr10, 1, implicit $exec
770-
; GFX90A-NEXT: renamable $vgpr52 = V_ALIGNBIT_B32_e64 $vgpr17, $vgpr16, 1, implicit $exec
769+
; GFX90A-NEXT: renamable $vgpr11 = V_ALIGNBIT_B32_opsel_e64 0, killed $sgpr47, 0, killed $vgpr10, 0, 1, 0, 0, implicit $exec
770+
; GFX90A-NEXT: renamable $vgpr52 = V_ALIGNBIT_B32_opsel_e64 0, $vgpr17, 0, $vgpr16, 0, 1, 0, 0, implicit $exec
771771
; GFX90A-NEXT: renamable $vgpr17 = V_CNDMASK_B32_e64 0, 0, 0, 1, $sgpr12_sgpr13, implicit $exec
772-
; GFX90A-NEXT: renamable $vgpr15 = V_ALIGNBIT_B32_e64 $vgpr15, $vgpr14, 1, implicit $exec
772+
; GFX90A-NEXT: renamable $vgpr15 = V_ALIGNBIT_B32_opsel_e64 0, $vgpr15, 0, $vgpr14, 0, 1, 0, 0, implicit $exec
773773
; GFX90A-NEXT: renamable $sgpr52_sgpr53 = S_XOR_B64 $exec, -1, implicit-def dead $scc
774774
; GFX90A-NEXT: renamable $sgpr62_sgpr63 = S_OR_B64 renamable $sgpr36_sgpr37, $exec, implicit-def dead $scc
775775
; GFX90A-NEXT: renamable $vgpr10 = COPY renamable $vgpr14, implicit $exec

‎llvm/test/MC/Disassembler/AMDGPU/gfx10_vop3.txt

Lines changed: 24 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1146,6 +1146,18 @@
11461146
# GFX10: v_alignbit_b32 v5, vcc_lo, v2, v3 ; encoding: [0x05,0x00,0x4e,0xd5,0x6a,0x04,0x0e,0x04]
11471147
0x05,0x00,0x4e,0xd5,0x6a,0x04,0x0e,0x04
11481148

1149+
# GFX10: v_alignbit_b32 v5, v1, v2, v3 op_sel:[1,0,0,0] ; encoding: [0x05,0x08,0x4e,0xd5,0x01,0x05,0x0e,0x04]
1150+
0x05,0x08,0x4e,0xd5,0x01,0x05,0x0e,0x04
1151+
1152+
# GFX10: v_alignbit_b32 v5, v1, v2, v3 op_sel:[1,1,0,0] ; encoding: [0x05,0x18,0x4e,0xd5,0x01,0x05,0x0e,0x04]
1153+
0x05,0x18,0x4e,0xd5,0x01,0x05,0x0e,0x04
1154+
1155+
# GFX10: v_alignbit_b32 v5, v1, v2, v3 op_sel:[1,1,1,0] ; encoding: [0x05,0x38,0x4e,0xd5,0x01,0x05,0x0e,0x04]
1156+
0x05,0x38,0x4e,0xd5,0x01,0x05,0x0e,0x04
1157+
1158+
# GFX10: v_alignbit_b32 v5, v1, v2, v3 op_sel:[1,1,1,1] ; encoding: [0x05,0x78,0x4e,0xd5,0x01,0x05,0x0e,0x04]
1159+
0x05,0x78,0x4e,0xd5,0x01,0x05,0x0e,0x04
1160+
11491161
# GFX10: v_alignbyte_b32 v255, v1, v2, v3 ; encoding: [0xff,0x00,0x4f,0xd5,0x01,0x05,0x0e,0x04]
11501162
0xff,0x00,0x4f,0xd5,0x01,0x05,0x0e,0x04
11511163

@@ -1233,6 +1245,18 @@
12331245
# GFX10: v_alignbyte_b32 v5, vcc_lo, v2, v3 ; encoding: [0x05,0x00,0x4f,0xd5,0x6a,0x04,0x0e,0x04]
12341246
0x05,0x00,0x4f,0xd5,0x6a,0x04,0x0e,0x04
12351247

1248+
# GFX10: v_alignbyte_b32 v5, v1, v2, v3 op_sel:[1,0,0,0] ; encoding: [0x05,0x08,0x4f,0xd5,0x01,0x05,0x0e,0x04]
1249+
0x05,0x08,0x4f,0xd5,0x01,0x05,0x0e,0x04
1250+
1251+
# GFX10: v_alignbyte_b32 v5, v1, v2, v3 op_sel:[1,1,0,0] ; encoding: [0x05,0x18,0x4f,0xd5,0x01,0x05,0x0e,0x04]
1252+
0x05,0x18,0x4f,0xd5,0x01,0x05,0x0e,0x04
1253+
1254+
# GFX10: v_alignbyte_b32 v5, v1, v2, v3 op_sel:[1,1,1,0] ; encoding: [0x05,0x38,0x4f,0xd5,0x01,0x05,0x0e,0x04]
1255+
0x05,0x38,0x4f,0xd5,0x01,0x05,0x0e,0x04
1256+
1257+
# GFX10: v_alignbyte_b32 v5, v1, v2, v3 op_sel:[1,1,1,1] ; encoding: [0x05,0x78,0x4f,0xd5,0x01,0x05,0x0e,0x04]
1258+
0x05,0x78,0x4f,0xd5,0x01,0x05,0x0e,0x04
1259+
12361260
# GFX10: v_and_b32_e64 v255, v1, v2 ; encoding: [0xff,0x00,0x1b,0xd5,0x01,0x05,0x02,0x00]
12371261
0xff,0x00,0x1b,0xd5,0x01,0x05,0x02,0x00
12381262

‎llvm/test/MC/Disassembler/AMDGPU/gfx9_vop3.txt

Lines changed: 24 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -11310,6 +11310,18 @@
1131011310
# CHECK: v_alignbit_b32 v5, v1, v2, exec_hi ; encoding: [0x05,0x00,0xce,0xd1,0x01,0x05,0xfe,0x01]
1131111311
0x05,0x00,0xce,0xd1,0x01,0x05,0xfe,0x01
1131211312

11313+
# CHECK: v_alignbit_b32 v5, v1, v2, v3 op_sel:[1,0,0,0] ; encoding: [0x05,0x08,0xce,0xd1,0x01,0x05,0x0e,0x04]
11314+
0x05,0x08,0xce,0xd1,0x01,0x05,0x0e,0x04
11315+
11316+
# CHECK: v_alignbit_b32 v5, v1, v2, v3 op_sel:[1,1,0,0] ; encoding: [0x05,0x18,0xce,0xd1,0x01,0x05,0x0e,0x04]
11317+
0x05,0x18,0xce,0xd1,0x01,0x05,0x0e,0x04
11318+
11319+
# CHECK: v_alignbit_b32 v5, v1, v2, v3 op_sel:[1,1,1,0] ; encoding: [0x05,0x38,0xce,0xd1,0x01,0x05,0x0e,0x04]
11320+
0x05,0x38,0xce,0xd1,0x01,0x05,0x0e,0x04
11321+
11322+
# CHECK: v_alignbit_b32 v5, v1, v2, v3 op_sel:[1,1,1,1] ; encoding: [0x05,0x78,0xce,0xd1,0x01,0x05,0x0e,0x04]
11323+
0x05,0x78,0xce,0xd1,0x01,0x05,0x0e,0x04
11324+
1131311325
# CHECK: v_alignbyte_b32 v5, v1, v2, v3 ; encoding: [0x05,0x00,0xcf,0xd1,0x01,0x05,0x0e,0x04]
1131411326
0x05,0x00,0xcf,0xd1,0x01,0x05,0x0e,0x04
1131511327

@@ -11406,6 +11418,18 @@
1140611418
# CHECK: v_alignbyte_b32 v5, v1, v2, exec_hi ; encoding: [0x05,0x00,0xcf,0xd1,0x01,0x05,0xfe,0x01]
1140711419
0x05,0x00,0xcf,0xd1,0x01,0x05,0xfe,0x01
1140811420

11421+
# CHECK: v_alignbyte_b32 v5, v1, v2, v3 op_sel:[1,0,0,0] ; encoding: [0x05,0x08,0xcf,0xd1,0x01,0x05,0x0e,0x04]
11422+
0x05,0x08,0xcf,0xd1,0x01,0x05,0x0e,0x04
11423+
11424+
# CHECK: v_alignbyte_b32 v5, v1, v2, v3 op_sel:[1,1,0,0] ; encoding: [0x05,0x18,0xcf,0xd1,0x01,0x05,0x0e,0x04]
11425+
0x05,0x18,0xcf,0xd1,0x01,0x05,0x0e,0x04
11426+
11427+
# CHECK: v_alignbyte_b32 v5, v1, v2, v3 op_sel:[1,1,1,0] ; encoding: [0x05,0x38,0xcf,0xd1,0x01,0x05,0x0e,0x04]
11428+
0x05,0x38,0xcf,0xd1,0x01,0x05,0x0e,0x04
11429+
11430+
# CHECK: v_alignbyte_b32 v5, v1, v2, v3 op_sel:[1,1,1,1] ; encoding: [0x05,0x78,0xcf,0xd1,0x01,0x05,0x0e,0x04]
11431+
0x05,0x78,0xcf,0xd1,0x01,0x05,0x0e,0x04
11432+
1140911433
# CHECK: v_min3_f32 v5, v1, v2, v3 ; encoding: [0x05,0x00,0xd0,0xd1,0x01,0x05,0x0e,0x04]
1141011434
0x05,0x00,0xd0,0xd1,0x01,0x05,0x0e,0x04
1141111435

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