Skip to content

Commit b17f4d3

Browse files
authored
[AggressiveInstCombine] Use AA during store merge (#149992)
This is a small extension of #147540, resolving one of the FIXMEs. Instead of bailing out on any instruction that may read/write memory, use AA to check whether it can alias the stored parts. Do this using a crude check based on the underlying object only. This pattern occurs rarely in practice, but at the same time it also doesn't seem to add any compile-time cost, so it's probably worth handling.
1 parent 7e878aa commit b17f4d3

File tree

2 files changed

+10
-14
lines changed

2 files changed

+10
-14
lines changed

llvm/lib/Transforms/AggressiveInstCombine/AggressiveInstCombine.cpp

Lines changed: 8 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -965,6 +965,7 @@ static bool foldConsecutiveStores(BasicBlock &BB, const DataLayout &DL,
965965
if (DL.isBigEndian())
966966
return false;
967967

968+
BatchAAResults BatchAA(AA);
968969
SmallVector<PartStore, 8> Parts;
969970
bool MadeChange = false;
970971
for (Instruction &I : make_early_inc_range(BB)) {
@@ -980,8 +981,13 @@ static bool foldConsecutiveStores(BasicBlock &BB, const DataLayout &DL,
980981
continue;
981982
}
982983

983-
// FIXME: Use AA to make this more precise.
984-
if (I.mayReadOrWriteMemory() || I.mayThrow()) {
984+
if (Parts.empty())
985+
continue;
986+
987+
if (I.mayThrow() ||
988+
(I.mayReadOrWriteMemory() &&
989+
isModOrRefSet(BatchAA.getModRefInfo(
990+
&I, MemoryLocation::getBeforeOrAfter(Parts[0].PtrBase))))) {
985991
MadeChange |= mergePartStores(Parts, DL, TTI);
986992
Parts.clear();
987993
continue;

llvm/test/Transforms/AggressiveInstCombine/X86/store-merge.ll

Lines changed: 2 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -359,13 +359,8 @@ define void @test_aliasing_store(i16 %x, ptr %p, ptr %p2) {
359359
define void @test_non_aliasing_store(i16 %x, ptr noalias %p, ptr noalias %p2) {
360360
; CHECK-LABEL: define void @test_non_aliasing_store(
361361
; CHECK-SAME: i16 [[X:%.*]], ptr noalias [[P:%.*]], ptr noalias [[P2:%.*]]) {
362-
; CHECK-NEXT: [[X_0:%.*]] = trunc i16 [[X]] to i8
363-
; CHECK-NEXT: store i8 [[X_0]], ptr [[P]], align 1
362+
; CHECK-NEXT: store i16 [[X]], ptr [[P]], align 1
364363
; CHECK-NEXT: store i8 0, ptr [[P2]], align 1
365-
; CHECK-NEXT: [[SHR_1:%.*]] = lshr i16 [[X]], 8
366-
; CHECK-NEXT: [[X_1:%.*]] = trunc i16 [[SHR_1]] to i8
367-
; CHECK-NEXT: [[GEP_1:%.*]] = getelementptr i8, ptr [[P]], i64 1
368-
; CHECK-NEXT: store i8 [[X_1]], ptr [[GEP_1]], align 1
369364
; CHECK-NEXT: ret void
370365
;
371366
%x.0 = trunc i16 %x to i8
@@ -403,13 +398,8 @@ define i8 @test_aliasing_load(i16 %x, ptr %p, ptr %p2) {
403398
define i8 @test_non_aliasing_load(i16 %x, ptr noalias %p, ptr noalias %p2) {
404399
; CHECK-LABEL: define i8 @test_non_aliasing_load(
405400
; CHECK-SAME: i16 [[X:%.*]], ptr noalias [[P:%.*]], ptr noalias [[P2:%.*]]) {
406-
; CHECK-NEXT: [[X_0:%.*]] = trunc i16 [[X]] to i8
407-
; CHECK-NEXT: store i8 [[X_0]], ptr [[P]], align 1
401+
; CHECK-NEXT: store i16 [[X]], ptr [[P]], align 1
408402
; CHECK-NEXT: [[V:%.*]] = load i8, ptr [[P2]], align 1
409-
; CHECK-NEXT: [[SHR_1:%.*]] = lshr i16 [[X]], 8
410-
; CHECK-NEXT: [[X_1:%.*]] = trunc i16 [[SHR_1]] to i8
411-
; CHECK-NEXT: [[GEP_1:%.*]] = getelementptr i8, ptr [[P]], i64 1
412-
; CHECK-NEXT: store i8 [[X_1]], ptr [[GEP_1]], align 1
413403
; CHECK-NEXT: ret i8 [[V]]
414404
;
415405
%x.0 = trunc i16 %x to i8

0 commit comments

Comments
 (0)