[LoongArch] Strengthen stack size estimation for LSX/LASX extension #146455
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@llvm/pr-subscribers-backend-loongarch Author: None (tangaac) ChangesFull diff: https://github.com/llvm/llvm-project/pull/146455.diff 2 Files Affected:
diff --git a/llvm/lib/Target/LoongArch/LoongArchRegisterInfo.cpp b/llvm/lib/Target/LoongArch/LoongArchRegisterInfo.cpp
index 47fce37ce59f6..b3a6ca9acad63 100644
--- a/llvm/lib/Target/LoongArch/LoongArchRegisterInfo.cpp
+++ b/llvm/lib/Target/LoongArch/LoongArchRegisterInfo.cpp
@@ -29,7 +29,6 @@ using namespace llvm;
#define GET_REGINFO_TARGET_DESC
#include "LoongArchGenRegisterInfo.inc"
-
LoongArchRegisterInfo::LoongArchRegisterInfo(unsigned HwMode)
: LoongArchGenRegisterInfo(LoongArch::R1, /*DwarfFlavour*/ 0,
/*EHFlavor*/ 0,
@@ -254,3 +253,15 @@ bool LoongArchRegisterInfo::canRealignStack(const MachineFunction &MF) const {
// reserve it.
return MRI->canReserveReg(LoongArchABI::getBPReg());
}
+
+bool LoongArchRegisterInfo::saveScavengerRegister(
+ MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
+ MachineBasicBlock::iterator &UseMI, const TargetRegisterClass *RC,
+ Register Reg) const {
+
+ DebugLoc DL;
+ const TargetInstrInfo &TII = *MBB.getParent()->getSubtarget().getInstrInfo();
+ TII.copyPhysReg(MBB, I, DL, LoongArch::R12, Reg, true);
+ TII.copyPhysReg(MBB, UseMI, DL, Reg, LoongArch::R12, true);
+ return true;
+}
\ No newline at end of file
diff --git a/llvm/lib/Target/LoongArch/LoongArchRegisterInfo.h b/llvm/lib/Target/LoongArch/LoongArchRegisterInfo.h
index d1e40254c2972..e9e7ee930f7f6 100644
--- a/llvm/lib/Target/LoongArch/LoongArchRegisterInfo.h
+++ b/llvm/lib/Target/LoongArch/LoongArchRegisterInfo.h
@@ -52,6 +52,11 @@ struct LoongArchRegisterInfo : public LoongArchGenRegisterInfo {
return true;
}
bool canRealignStack(const MachineFunction &MF) const override;
+ bool saveScavengerRegister(MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator I,
+ MachineBasicBlock::iterator &UseMI,
+ const TargetRegisterClass *RC,
+ Register Reg) const override;
};
} // end namespace llvm
|
tangaac
changed the title
heiher
reviewed
Jul 8, 2025
|
reduced.ll.txt |
SixWeining
reviewed
Jul 16, 2025
| @@ -47,7 +47,7 @@ define i64 @va1(ptr %fmt, ...) { | |||
| ; LA64-WITHFP-NEXT: st.d $a2, $fp, 16 | |||
| ; LA64-WITHFP-NEXT: st.d $a1, $fp, 8 | |||
| ; LA64-WITHFP-NEXT: addi.d $a1, $fp, 16 | |||
| ; LA64-WITHFP-NEXT: st.d $a1, $fp, -24 | |||
There was a problem hiding this comment.
With this PR or not, there is no difference between debugging outputs.
So it's ok to ignore this change.
SixWeining
approved these changes
Jul 18, 2025
|
/cherry-pick 64a0478 |
|
/pull-request #149777 |
heiher
pushed a commit
to llvmbot/llvm-project
that referenced
this pull request
Jul 23, 2025
…lvm#146455) This patch adds an emergency spill slot when ran out of registers. PR llvm#139201 introduces `vstelm` instructions with only 8-bit imm offset, it causes no spill slot to store the spill registers. (cherry picked from commit 64a0478)
tru
pushed a commit
to llvmbot/llvm-project
that referenced
this pull request
Jul 24, 2025
…lvm#146455) This patch adds an emergency spill slot when ran out of registers. PR llvm#139201 introduces `vstelm` instructions with only 8-bit imm offset, it causes no spill slot to store the spill registers. (cherry picked from commit 64a0478)
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This patch adds an emergency spill slot when ran out of registers.
PR #139201 introduces
vstelminstructions with only 8-bit imm offset,it causes no spill slot to store the spill registers.