Skip to content

[RISCV][FPE] Remove unused variable #149054

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
merged 1 commit into from
Jul 16, 2025
Merged

[RISCV][FPE] Remove unused variable #149054

merged 1 commit into from
Jul 16, 2025

Conversation

spavloff
Copy link
Collaborator

It was added by me in 905bb5b, which committed PR #148569.

It was added by me in 905bb5b,
which committed PR llvm#148569.
@spavloff spavloff self-assigned this Jul 16, 2025
@llvmbot
Copy link
Member

llvmbot commented Jul 16, 2025

@llvm/pr-subscribers-backend-risc-v

Author: Serge Pavlov (spavloff)

Changes

It was added by me in 905bb5b, which committed PR #148569.


Full diff: https://github.com/llvm/llvm-project/pull/149054.diff

1 Files Affected:

  • (modified) llvm/lib/Target/RISCV/RISCVISelLowering.cpp (-1)
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index de830666d89b8..0cee5c87e999d 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -14021,7 +14021,6 @@ SDValue RISCVTargetLowering::lowerGET_FPMODE(SDValue Op,
   SDLoc DL(Op);
   SDValue Chain = Op->getOperand(0);
   SDValue SysRegNo = DAG.getTargetConstant(RISCVSysReg::fcsr, DL, XLenVT);
-  SDValue ModeMask = DAG.getConstant(ModeMaskValue, DL, XLenVT);
   SDVTList VTs = DAG.getVTList(XLenVT, MVT::Other);
   SDValue Result = DAG.getNode(RISCVISD::READ_CSR, DL, VTs, Chain, SysRegNo);
   Chain = Result.getValue(1);

@spavloff spavloff merged commit c71b92d into llvm:main Jul 16, 2025
11 checks passed
@spavloff spavloff deleted the riscv.mode2 branch July 16, 2025 12:56
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Projects
None yet
Development

Successfully merging this pull request may close these issues.

2 participants