AMDGPU: Remove the dot4 test in insert-delay-alu-wmma-xdl.mir, NFC

[changpeng]

This is irrelevant, and caused a failure in downstream.

Fixes: SWDEV-544025

[llvmbot]

@llvm/pr-subscribers-backend-amdgpu

Author: Changpeng Fang (changpeng)

Changes

This is irrelevant, and caused a failure in downstream.

---

Full diff: https://github.com/llvm/llvm-project/pull/149375.diff

1 Files Affected:

• (modified) llvm/test/CodeGen/AMDGPU/insert-delay-alu-wmma-xdl.mir (-17)

diff --git a/llvm/test/CodeGen/AMDGPU/insert-delay-alu-wmma-xdl.mir b/llvm/test/CodeGen/AMDGPU/insert-delay-alu-wmma-xdl.mir
index 7c3170d8d1e9f..0abf34797a5e7 100644
--- a/llvm/test/CodeGen/AMDGPU/insert-delay-alu-wmma-xdl.mir
+++ b/llvm/test/CodeGen/AMDGPU/insert-delay-alu-wmma-xdl.mir
@@ -65,20 +65,3 @@ body: |
     $vgpr12 = V_EXP_F32_e32 $vgpr12, implicit $exec, implicit $mode
     $vgpr13 = V_ADD_U32_e32 $vgpr13, $vgpr8, implicit $exec
 ...
-
----
-name: dot_xdl_dep_2
-tracksRegLiveness: true
-body: |
-  bb.0:
-    ; CHECK-LABEL: {{^}}dot_xdl_dep_2:
-    ; CHECK: %bb.0:
-    ; CHECK-NEXT: v_dot4_i32_iu8 v0, s2, s3, v0 neg_lo:[1,1,0]
-    ; CHECK-NEXT: v_dot4_i32_iu8 v1, s2, s3, v2 neg_lo:[1,1,0]
-    ; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_2)
-    ; CHECK-NEXT: v_add_nc_u32_e32 v2, v0, v0
-    liveins: $vgpr0, $sgpr2, $sgpr3, $vgpr0, $vgpr1, $vgpr2
-    $vgpr0 = V_DOT4_I32_IU8 9, $sgpr2, 9, $sgpr3, 8, $vgpr0, 0, 0, 0, implicit $exec
-    $vgpr1 = V_DOT4_I32_IU8 9, $sgpr2, 9, $sgpr3, 8, $vgpr2, 0, 0, 0, implicit $exec
-    $vgpr2 = V_ADD_U32_e32 $vgpr0, $vgpr0, implicit $exec
-...

[shiltian]

Honestly I don't follow…

[changpeng]

Honestly I don't follow…
This is related to PR: #149208, specifically the following piece of code:

// WMMA XDL ops are treated the same as TRANS.
if (AMDGPU::isGFX1250(*ST) && SII->isXDLWMMA(MI))
return TRANS;

The DOT instruction test is not relevant. But this test is causing a failure in one of the downstream branch.
The reason the DOT instruction check was there is because people once though DOT can also be treated as a TRAN,
and later confirmed not. Thus that is in an intermediate state.

[arsenm]

Honestly I don't follow…
This is related to PR: #149208, specifically the following piece of code:

// WMMA XDL ops are treated the same as TRANS. if (AMDGPU::isGFX1250(*ST) && SII->isXDLWMMA(MI)) return TRANS;

The DOT instruction test is not relevant. But this test is causing a failure in one of the downstream branch. The reason the DOT instruction check was there is because people once though DOT can also be treated as a TRAN, and later confirmed not. Thus that is in an intermediate state.

Then the test should remain as a negative test

[changpeng]

Honestly I don't follow…
This is related to PR: #149208, specifically the following piece of code:

// WMMA XDL ops are treated the same as TRANS. if (AMDGPU::isGFX1250(*ST) && SII->isXDLWMMA(MI)) return TRANS;
The DOT instruction test is not relevant. But this test is causing a failure in one of the downstream branch. The reason the DOT instruction check was there is because people once though DOT can also be treated as a TRAN, and later confirmed not. Thus that is in an intermediate state.

Then the test should remain as a negative test
The failure is root-caused to instruction format changes, and has been exposed by other tests already. @jun Wang is working on it. We should not keep the test in a irrelevant category.