CPU Design project for the course "Application and Design of Digital Logic" at Glasgow College, UESTC .
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Nov 23, 2024 - VHDL
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fsm
A finite-state machine (FSM), finite-state automaton (FSA), or simply state machine is a mathematical model of computation and an abstract machine that can be in exactly one of a finite number of states at any given time.
The FSM can change from one state to another in response to some inputs; the change from one state to another is called a transition.
An FSM is defined by a list of its states, its initial state, and the inputs that trigger each transition.
In computer science, FSM are widely used in modeling of application behavior (control theory), design of hardware digital systems, software engineering, compilers, network protocols, and computational linguistics.
Here are 35 public repositories matching this topic...
Signed / unsigned multiplier / divider used by a microcode-driven prime number generator
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Apr 7, 2018 - VHDL
💻 Repositório para Disciplina EEL5105 - Circuitos e Técnicas Digitais - UFSC
language counter fsm register digital hardware clock timer machine vhdl circuits description sequential multiplexer techniques quartus flip-flop multisim latch combinational
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Apr 3, 2020 - VHDL
Simple calculator implemented in VHDL using FSM logic
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Aug 24, 2019 - VHDL
VHDL codes for 8-bit Vending Machine Processor, support for two drinks & three types of coins. contains: fsm, Accumulator, comparator, subtractor, mux, Adder, etc.
fsm fpga processor vhdl mux vendingmachine comparator accumulator vending-machine vhdl-code full-adder
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Jul 20, 2021 - VHDL
VHDL Implementation of Modulo2 Line by Matrix Multiplication (with Tutorial Series on Steemit)
c fsm vhdl multiplication accumulator multiplication-algorithm control-signals modulo2 hardware-design
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Oct 19, 2020 - VHDL
Integrated and programmed a VGA Interface using the Altera DE1 to output in synchronization with a custom programmed finite-state machine.
fsm vhdl intel finite-state-machine quartus-prime vga-driver vga-controller altera-fpga vhdl-coursework quartus2 altera-de1
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Feb 7, 2023 - VHDL
Projekt (UART přijímací část) z předmětu Návrh číslicových systémů (INC), druhý semestr bakalářského studia BIT na FIT VUT/BUT, ak.rok 2021/2022
fsm fpga vhdl university-project xilinx uart xilinx-fpga vutbr vut vhdl-code vut-fit vhdl-coursework uart-receiver brno-university-of-technology
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Jan 12, 2024 - VHDL
Final project of Logical Networks course - Politecnico di Milano 2022/23
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Sep 8, 2023 - VHDL
Finite-State Machine Design of a Simple Car Security Alarm on FPGA
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Feb 6, 2020 - VHDL
Flappy Bird VHDL
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Jan 11, 2022 - VHDL
4-bit calculator with all operations we set up for calculator. It have some main parts which are FSM(Finite State Machine) which has MOP(Micro-operations). Datapath that includes calculator's brain which is ALU(Arithmetic Logic Unit), multiplexers and hexadecimal decoder.
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Oct 22, 2023 - VHDL
FSM and Cache design for practicing the concepts of computer architecture
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May 1, 2021 - VHDL
Prova Finale di Reti Logiche - Polimi Ingegneria Informatica - A.A. 2019-2020
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Oct 11, 2020 - VHDL
Computer Architecture Project using VHDL
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Jun 19, 2024 - VHDL
This repository showcases various projects developed on the DE10-Lite board (Intel MAX 10 FPGA) using Quartus Prime Lite software. The projects primarily focus on Finite State Machines (FSMs) and communication protocols, implemented in VHDL. Each project includes HDL code, testbenches, simulations, and qsf files for pin assignments.
microcontroller fsm dsp vhdl verification gtkwave testbenches verilog-hdl digital-circuits pin-assignment uart-vhdl qsf rtl-simulations ip-cores
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Sep 6, 2024 - VHDL
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