i8080 precise replica in Verilog, based on reverse engineering of real die
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Jul 13, 2019 - Verilog
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microprocessor
Here are 31 public repositories matching this topic...
5-stage pipelined 32-bit MIPS microprocessor in Verilog
verilog microprocessor computer-architecture microprocessors verilog-hdl mips-architecture mips-processor bits-pilani computer-organization verilog-components verilog-snippets mips-instructions computer-organisation verilog-programs verilog-simulator verilog-project
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Apr 3, 2020 - Verilog
RISC-V Embedded Processor for Approximate Computing
cpu fpga embedded-systems riscv microprocessor computer-architecture vlsi risc-v approximate-computing cpu-design
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May 30, 2025 - Verilog
CoPHEE is a Co-processor for Partially Homomorphic Encrypted Encryption.
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Feb 21, 2024 - Verilog
This repository contain the implementaton of RV32I 5-Stage-Pipeline-Processor based on RISC-V ISA and designed on Verilog
vhdl verilog microprocessor vivado hardware-designs computer-architecture gtkwave vlsi pipeline-processor risc-v rv32i verilator rv32im asic-design chip-design 5-stage-pipelined-processor rv32i-processor
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Feb 19, 2025 - Verilog
Fully pipelined DLX Microprocessor optimized for energy efficiency and testing purposes developed in VHDL. Simulation with Intel® ModelSim®, synthesis under Synopsys® DC Ultra™, and physical layout using Cadence® Innovus™ Implementation System.
optimization polito microprocessor synthesis synopsys dlx cadence digital-design physical-design dlx-microprocessor
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Jun 9, 2021 - Verilog
RISC based 8-bits five stage pipelined processor, operating at 585 MHz clock frequency with 19 I/O pins and 28 instructions having 5 Addressing formats. Tested on Xilinx Artix-7 FPGA.
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Sep 3, 2020 - Verilog
This repository contains the implementation of single cycle processor based on RISC-V ISA and implemented on "LOGISIM".
vhdl verilog microprocessor hardware-designs computer-architecture pipeline-processor rv32i single-cycle-processor 5-stage-pipeline 3-stagepipeline fetch-stage-pipeline
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May 24, 2024 - Verilog
DLX microprocessor described in VHDL for the Microelectronic Systems course @ Politecnico di Torino
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Jan 16, 2023 - Verilog
A single cycle MIPS RISC-V CPU Core using Verilog
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Feb 12, 2023 - Verilog
32-Bit Processor, formerly 8-bit
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Apr 1, 2023 - Verilog
This repo is implementation of 32 bit RISC -V based processor in verilog with 5 stage pipelining
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Mar 3, 2022 - Verilog
VHDL(Verilog Hardware Description Language) is a programming language using which one can simulate hardware circuits
controller vhdl verilog microprocessor mux add alu risc hdl multiplexer sub 8-bit program-counter bitwise-or bitwise-and
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Jul 30, 2020 - Verilog
DLX processor implementation and improvement
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Jul 18, 2017 - Verilog
The IPPro is a 16-bit signed fixed-point, five-stage balanced pipelined RISC architecture that exploits the DSP48E1 features and provides balance among performance, latency and efficient resource utilization.
fpga processor image-processing microprocessor datapath risc hardware-acceleration softcore xilinx-zynq pipelined-processors ippro
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Feb 14, 2023 - Verilog
Implementation of a basic RISC microprocessor based on ARM architecture. Course project for ICOM4215.
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May 20, 2020 - Verilog
32-bit 5-stage RISC Microprocessor implementation in Verilog
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May 26, 2023 - Verilog
A Verilog implementation of the LC3 (Little Computer 3) micro-architecture/ISA as described in "Introduction to Computing Systems" by Patt & Patel.
hardware rtl verilog microprocessor computer-architecture instruction-set-architecture microarchitecture
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May 25, 2025 - Verilog
This project is an improvement on a microprocessor done in class.
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Feb 27, 2020 - Verilog
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