Rule110 Cellular Automata ASIC for Tiny Tapeout 05
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Nov 9, 2023 - Verilog
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pseudo-random-generator
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Digital Design and Computer Organisation Mini-project
arm fpga project verilog college-project digital-design computer-organization prbs-generator mini-project sequence-generation pseudo-random-generator field-programmable-gate-arrays verilog-project sequence-generator prbs ddco arm7tdmi digital-design-and-computer-organization binary-sequence-generator
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Aug 7, 2023 - Verilog
5-bit Galois Linear Feedback Shift Register for pseudo-random sequence generation. Implements maximal-length sequence (31 states) suitable for cryptographic applications, BIST mechanisms, and data scrambling with comprehensive waveform verification.
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Aug 6, 2025 - Verilog
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