single-cycle-processor

Here are 31 public repositories matching this topic...

aofarmakis / Nibbling-bits

Design and documentation for a very simple 4-bit processor named NibbleBuddy and its assembler.

assembly assembler verilog computer-architecture instruction-set-architecture computer-organization hardware-description-language processor-design single-cycle-processor

Updated Dec 7, 2024
Verilog

phillbush / legv8

Star

LEGv8 CPU implementation and some tools like a LEGv8 assembler

awk verilog pipeline-processor pipeline-cpu single-cycle hennessy patterson legv8-arm legv8 single-cycle-processor hennessy-and-patterson

Updated Nov 28, 2020
Verilog

PebPeb / Single-Cycle-RV32I

Star

Single Cycle CPU using the RV32I Base Instruction set

cpu computer-architecture from-scratch risc-v single-cycle-processor

Updated Jul 15, 2023
Verilog

explcre / 21Summer-VE370-Intro-to-Computer-Organization-Projects

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21Summer-VE370-Intro-to-Computer-Organization-Projects: -Project1: RISC-V Assembly, simluating c code. -Project2: 1.RISC-V64 single cycle processor. 2.RISC-V64 five-stage pipelined processor. -Project3: Virtual memory, TLB, cache, memory simulator. -Project4: Literature review on Computer Organization.

cpu virtual-memory tlb risc-v cpu-emulator computer-organization tlb-simulator riscv64 computer-organisation-architechure risc-v-assembly single-cycle-processor 5-stage-pipeline computer-organization-lab computer-organization-and-design

Updated Apr 11, 2023
Verilog

SnrNotHere16 / RISCVSingleCycleProcessor

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A RISC-V Single Cycle Processor which is done in verilog.

module verilog vivado computer-architecture risc-v 32-bit hardware-description-language riscv32 risc-architecture-processor single-cycle-processor testbench-generator-verilog

Updated Jul 20, 2020
Verilog

arsalanjabbari / MIPS-CPU-Design

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This project involves the creation of a single-cycle MIPS CPU design using Verilog. The single-cycle microarchitecture is characterized by executing an entire instruction in one clock cycle. The project delves into the intricacies of designing and implementing a simplified MIPS CPU, providing insights into its fundamental components.

mips cpu-design single-cycle-processor

Updated Aug 14, 2023
Verilog

arhamhashmi01 / RV32I_Single_Cycle

Star

This repository contains the implementation of single cycle processor based on RISC-V ISA and implemented on "LOGISIM".

vhdl verilog microprocessor hardware-designs computer-architecture pipeline-processor rv32i single-cycle-processor 5-stage-pipeline 3-stagepipeline fetch-stage-pipeline

Updated May 24, 2024
Verilog

OmarAmer01 / VP_Harvard_MIPS

Star

A 32-bit microprocessor with 42 instructions (including multiplication and division) and 8 X 32 registers and 2048 X 32 Ram with shared stack. An assembler is also available to write programs on the microprocessor using 8086-like assembly.

mips verilog computer-architecture vlsi modelsim single-cycle-processor

Updated Feb 19, 2022
Verilog

Visheshanagu2894 / riscv

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RISC-V 32IM - Dobby SOC

pipeline riscv32 booths-algorithm risc-v-assembly single-cycle-processor risc-v32im

Updated Jul 1, 2022
Verilog

muhammadtalhasami / RV32I_Single_Cycle

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This repository contains an implementation of a RV32I fetch pipeline microprocessor. The RV32I is a 32-bit RISC-V instruction set architecture, with the 'I' extension indicating the base integer instructions.

Updated Aug 10, 2024
Verilog

ntsdwkr / MIPS

Star

Single Cycle MIPS (RISC) Processor

mips verilog risc risc-v mips32 single-cycle-processor

Updated Jan 30, 2024
Verilog

MaheenAnees / Single-Cycle-RISCV-Processor

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This repository is created to build a single cycle processor and converting it to a 5-stage pipelined processor capable of executing a bubble sort program.

verilog computer-architecture risc-v pipelined-processors single-cycle-processor