SystemC/TLM-2.0 Co-simulation framework
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Updated
May 21, 2025 - Verilog
SystemC/TLM-2.0 Co-simulation framework
Basic RISC-V Test SoC
This project provide the necessary to run a env test a simple uart verilog using SystemC and running it on icarus verilog
Inference Design, Behavioral simulations, and Hardware Implementation.
Emulation, implementation and verification of RISC-V core with I,M and Zbb extensions
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