RTL data structure
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Jul 30, 2025 - SystemVerilog
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verilog-hdl
Here are 39 public repositories matching this topic...
RTL design and implementation of a 4x4 Network-on-Chip (NoC) with a mesh topology. This project includes SystemVerilog modules for buffer units, routing units, switch allocators, switches, routers, and nodes, along with comprehensive high-level testing scenarios. Developed as part of a Core-Based Embedded System Design course.
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Jul 12, 2024 - SystemVerilog
Trying to learn Wishbone by implementing few master/slave devices
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Jan 7, 2019 - SystemVerilog
BDD Gherkin implementation in native SystemVerilog, based on UVM.
asic fpga bdd bdd-specs rtl verilog systemverilog uvm verilog-hdl bdd-framework asic-verification design-verification asic-design rtl-design soc-design soc-verification uvm-verification
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Nov 16, 2024 - SystemVerilog
A Verilog I2C initializer with integrated RS232 debugger. *** New v1.1 Supports I2C CLK stretch and separate IO buffers for driving Efinix's IO primitive.
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Jun 26, 2023 - SystemVerilog
Submission for Tiny Tapeout 8 - Verilog HDL Projects. An adder with a separate flow control for each argument and the result.
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Sep 5, 2024 - SystemVerilog
KL10PV (also called "model B") CPU implemented in SystemVerilog for Xilinx FPGA from MP00301_KL10PV_Jun80 PDFs trying to remain faithful to the original while I learn Verilog
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Jun 12, 2020 - SystemVerilog
Verilog Codes of various Inter Device Communication Protocols
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Apr 28, 2018 - SystemVerilog
This testbench is based on SV and UVM Class based to verify Verilog HDL Design
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Mar 23, 2023 - SystemVerilog
Creating a risc-v processor
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Apr 4, 2024 - SystemVerilog
An attempt at making a customised RISC processor with five pipelined stages and supporting all RISC-V instruction set
linux arm assembly intel riscv verilog hdl verilog-hdl risc-v quartus-prime systemverilog-hdl riscv32
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May 13, 2023 - SystemVerilog
VerilogHDL implementation of One-Time Password Algorithm (HOTP)
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Oct 29, 2022 - SystemVerilog
Mips Multi-Cycle, Computer Architecture course, University of Tehran
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Aug 4, 2020 - SystemVerilog
IceCream for SystemVerilog: Never use $display and `uvm_info to debug SystemVerilog again.
debugging debug systemverilog verilog-hdl icecream debugging-tools systemverilog-hdl systemverilog-simulation systemverilog-developer systemverilog-test-bench
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Aug 19, 2024 - SystemVerilog
Verilog Codes for various Design
pipeline multiplication verilog fifo uvm adder system-verilog verilog-hdl max-pooling sequence-detector one-detector reconfigurable-matrix-adder
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Nov 24, 2023 - SystemVerilog
ROCC accelerator ISA based neuroSynapse
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Nov 3, 2021 - SystemVerilog
Implementation of a generalized Parallel Multiplier using Carry Save Adder in SystemVerilog and Xilinx Vivado.
asic fpga rtl systemverilog verilog-hdl xilinx-vivado multiplier fpga-programming vlsi-design asic-design rtl-design parallel-multiplication systemverilog-test-bench register-transfer-level
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Jun 19, 2025 - SystemVerilog
Verification of D-FF using UVM on EDA playground
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Nov 19, 2023 - SystemVerilog
UP_Counter_4bit_Verification_with_UVM
coverage counter scoreboard testcase scenario sequence systemverilog synopsys uvm verilog-hdl uvm-verification
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Jun 17, 2025 - SystemVerilog
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