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arch-hexagonQualcomm Hexagon DSPQualcomm Hexagon DSParch-loongarch32-bit and 64-bit LoongArch32-bit and 64-bit LoongArcharch-mips32-bit and 64-bit MIPS32-bit and 64-bit MIPSarch-powerpc32-bit and 64-bit Power ISA32-bit and 64-bit Power ISAarch-s390x64-bit IBM z/Architecture64-bit IBM z/Architecturearch-wasm32-bit and 64-bit WebAssembly32-bit and 64-bit WebAssemblybackend-llvmThe LLVM backend outputs an LLVM IR Module.The LLVM backend outputs an LLVM IR Module.bugObserved behavior contradicts documented or intended behaviorObserved behavior contradicts documented or intended behaviorenhancementSolving this issue will likely involve adding new logic or components to the codebase.Solving this issue will likely involve adding new logic or components to the codebase.standard libraryThis issue involves writing Zig code for the standard library.This issue involves writing Zig code for the standard library.upstreamAn issue with a third party project that Zig uses.An issue with a third party project that Zig uses.zig ccZig as a drop-in C compiler featureZig as a drop-in C compiler feature
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We've accumulated a number of issues that should be addressed with LLVM 20, so just opening this as a meta issue to track them all in one place:
- Compiler crash when targeting
mips64
when returningfp128
after calling a function returning{ i8, i128 }
llvm/llvm-project#96432 - [Hexagon][Docs] document the change in the default target llvm/llvm-project#125584
- Send patch to LLVM adding the muslabin32 target environment #2909
- [WebAssembly]
memcpy
does not result in no-op for zero-length slices #16360 -
behavior.vector.test.vector float operators
causes LLVM assertion failure onmips*-linux-*
#21051 - Remove "slow target" flag for
mips(el)-linux
targets in tests with LLVM 20 #21096 - Re-enable FastISel for MIPS O32 with LLVM 20 #21215
- Remove
s390x-linux-gnu
assembler workarounds with LLVM 20 #21329 - Remove the PowerPC soft float preprocessor workaround with LLVM 20 #21411
- Update our baseline and generic CPU models for WebAssembly #21818
- Remove the LoongArch
f16
lowering workaround with LLVM 20 #22003 - Enable red zone support for PowerPC after the LLVM 20 upgrade #23056
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Lines 273 to 274 in a9c7714
.muslabin32 => "musl", // Should be muslabin32 in LLVM 20. .muslabi64 => "musl", // Should be muslabi64 in LLVM 20. -
Lines 2266 to 2273 in a9c7714
.aarch64, .aarch64_be, .loongarch64, // TODO: `-sp` and `-sf` ABI support in LLVM 20. .m68k, .powerpc64, .powerpc64le, .s390x, => |arch| if (abi == .musl) initFmt("/lib/ld-musl-{s}.so.1", .{@tagName(arch)}) else none,
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arch-hexagonQualcomm Hexagon DSPQualcomm Hexagon DSParch-loongarch32-bit and 64-bit LoongArch32-bit and 64-bit LoongArcharch-mips32-bit and 64-bit MIPS32-bit and 64-bit MIPSarch-powerpc32-bit and 64-bit Power ISA32-bit and 64-bit Power ISAarch-s390x64-bit IBM z/Architecture64-bit IBM z/Architecturearch-wasm32-bit and 64-bit WebAssembly32-bit and 64-bit WebAssemblybackend-llvmThe LLVM backend outputs an LLVM IR Module.The LLVM backend outputs an LLVM IR Module.bugObserved behavior contradicts documented or intended behaviorObserved behavior contradicts documented or intended behaviorenhancementSolving this issue will likely involve adding new logic or components to the codebase.Solving this issue will likely involve adding new logic or components to the codebase.standard libraryThis issue involves writing Zig code for the standard library.This issue involves writing Zig code for the standard library.upstreamAn issue with a third party project that Zig uses.An issue with a third party project that Zig uses.zig ccZig as a drop-in C compiler featureZig as a drop-in C compiler feature